The present invention relates to a semiconductor memory device including a redundancy memory cell, and more particularly, to a dynamic column redundancy driving circuit for a semiconductor memory device.
A semiconductor memory device includes a memory cell array arranged in the matrix form and is manufactured by a fabrication process of a semiconductor. However, as the memory becomes highly integrated, it is difficult to normally form all cells consisting of a semiconductor memory device due to characteristics of the fabrication process of a semiconductor. Accordingly, in order to increase the yield of the semiconductor memory device, it is required that a redundancy memory cell is formed and the redundancy memory cell is used instead of a memory cell having a defect. In the scheme using the redundancy memory cell, a coding method by a fuse is usually used. Here, processes of test and repair performed after a fabrication process of a semiconductor will be described.
In the semiconductor memory device, the predetermined number of memory cells are driven by one word line, and each word line is activated selectively according to each address applied from the outside. The word lines for driving the normal memory cells are physically fabricated such that each one corresponds to one address applied from the outside. In the redundancy word line for driving the redundancy memory cell, the address is not determined in a fabrication process, but fuse boxes programmable according to a defect address are formed in each redundancy word line. As a result of the test, when defect is found in a normal memory cell, a word line for driving the normal memory cell is disconnected and a fuse box of the redundancy word line is programmable according to the address (defect address) of the disconnected word line. The fuse box includes a plurality of fuses, where a pair of fuses are formed in per bit consisting of the address and one of each pair of fuses is selectively disconnected according to its bit information of the defect address.
The redundancy word line having the fuse box programmed by the above method is activated when an address applied from outside of a semiconductor chip matches its defect address, to thereby drive a plurality of redundancy memory cells coupled to the redundancy word line. A column redundancy driving circuit of a semiconductor memory device is to determine whether the address applied from the outside matches the defect address, to thereby drive the corresponding redundancy word line. Also, the column redundancy driving circuit is divided into a dynamic type and a static type.
FIG. 1 shows a conventional dynamic column redundancy driving circuit of a synchronous semiconductor memory device, and FIG. 2 is timing diagrams of each signal shown in FIG. 1. Referring to FIGS. 1 and 2, a node "K" is boosted to a supply voltage VCC level by a precharging portion 110 when a clock CLK is "low". When the clock CLK is "low", a PMOS transistor 111 is on, the node "K" becomes "high" and then "high" level of node "K" is inverted by an inverter 113 to be applied to a gate of the PMOS transistor 112. In an address determining portion 120, when address signals (AO, A1, . . . , Ai) correspond to the defect address, the level of the node "K" is maintained in "high", otherwise, the level of the node "K" is changed to "low". In a driving portion 130, the signal of the node "K" is buffered, to thereby produce a redundancy word line driving signal REDi. The dynamic column redundancy driving circuit has a small layout area However, the node "K" should be precharged after resetting the address. That is, a time interval is required between the resetting and the precharging. This time interval serves as an obstacle for high-speed operation. Accordingly, the circuit is inappropriate to the synchronous dynamic random access memory device for high speed operation.
FIG. 3 shows another conventional static column redundancy driving circuit of a synchronous semiconductor memory device, and FIG. 4 is timing diagrams of each signal shown in FIG. 3. Referring to FIGS. 3 and 4, an address determining portion 210 includes a plurality of transmission gates 211A, 212A, . . . , 213A for receiving address signals A0, A1, . . . , Ai, a plurality of transmission gates 211B, 212B,. . . , 213B for receiving inverted address signals A0B, A1B,. . . , AiB, and a plurality of fuses FA0, FA1, . . . , FAi and FB0, FB1, . . . , FBi programmed according to the defect address. A pull-down portion 220 includes a plurality of NMOS transistors 221, 222 and 223. A driving portion 230 performs logical AND operation of logic levels of each node "L0", "L1",. . . , "Li" to thereby produce the redundancy word line driving signal REDi. The driving portion 230 may include multiple stages of logic gate, where a first stage includes two input NAND gates 231 and 232, a second stage includes two input-NOR gates 233 and 234, a third stage includes two input-NAND gate 235, and a fourth stage includes an inverter 236. A master fuse 250 is in a connection state in case that the corresponding redundancy memory cell replaces the defective memory cell, otherwise, the master fuse 250 is disconnected during test and repair process. When address signals A0, A1,. . . , Ai are applied from the outside and a driving enable signal VINT is "high", the driving enable signal VINT is inverted by an inverter 241 and a "low" level is applied to a gate of the PMOS transistor 240 and a gate of the NMOS transistor 261, to thereby turn-on the PMOS transistor 240 and turn-off the NMOS transistor 261. Accordingly, a drain of the NMOS transistor 261 becomes "high", which is inverted by an inverter 263. At this time, the node "K" becomes "low" and then each transmission gate 211A, 211B, 212A, 212B, 213A and 213B of the address determining portion 120 transmits the address signals A0, A1,. . . , Ai and the inverted addresses A0B, A1B,. . . , Ai, and the NMOS transistors 221, 222 and 223 of the pull-down portion 220 are off. An inverter 264 inverts the level of the node "K" to apply to each gate of the NMOS transistors forming each transmission gate. Accordingly, each level of the nodes L0, L1,. . . , Li is different based on a disconnection state of each fuse FA0, FA1,. . . , FAi and FB0, FBi,. . . , FBi. In detail, in case that the address signals A0, A1,. . . , Ai matches the defect address, each level of the nodes L0, L1, . . . , Li is "high" and a level of the redundancy word line driving signal REDi becomes also "high". The static column redundancy driving circuit, which does not need to reset addresses or precharge a predetermined node unlike the column redundancy driving circuit shown in FIG. 1, is appropriate for operation at high speed. However, it requires a large layout area.
FIG. 5 shows still another conventional dynamic column redundancy driving circuit of a synchronous semiconductor memory device, and FIG. 6 is a timing diagram of each signal shown in FIG. 5. Referring to FIGS. 5 and 6, a precharging portion 310 includes two PMOS transistors 311 and 312 and an inverter 313, and an address determining portion 320 includes a plurality of fuses FA0, FA1, . . . , FAi and FB0, FB1, . . . , FBi programmed according to the defect address, a plurality of NMOS transistors 321A, 322A, 323A, 321B, 322B and 323B and a pull-down transistor 325 for receiving address signals A0, A1,. . . , Ai and inverted addresses A0B, A1B,. . . , AiB. A discharge portion 330 includes an inverter 312 and a NMOS transistor 331. When an enable signal VINT is "low", the output of the inverter 312 becomes "high", and the NMOS transistor 331 is on. When the NMOS transistor 331 is on, the level of the node "K" is "low". A latch portion 340 includes two inverters 341 and 342, and an inverter 350 drives the output of the latch portion 340. Also, a transmission gate 360 including a PMOS transistor 361, a NMOS transistor 362 and an inverter 363 is on when the clock CLK is "high", to thereby transmit the output of the node "K" to a node "K1".
However, in the dynamic column redundancy driving circuit shown in FIG. 5, the node "K1" should be discharged before the transmission gate 360 is on to transmit a signal of the node "K" to the latch portion 340. In case that the transmission gate 360 is on before the node "K1" is sufficiently discharged, skew occurs to generate malfunction. Also, the transmission gate 360, the discharge portion 330 and the latch portion 340 are included, to thereby increase the layout area, and further signal delay may occur due to the transmission gate 360 controlled by the clock CLK.